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512mb: x4, x8, x16 ddr sdram pdf=09005aef80c1 b136 / source=09005aef80c1a8c0 512mb: x4, x8, x16 ddr sdram rev: 11/24/2004 0 www.spectek.com spectek reserves the right to change products or specifications without notice. 2003 , 2004 spectek double data rate (ddr) sdram features pc2100, pc2700 and pc3200 compatible vdd = +2.5v 0.2v, vddq = +2.5v 0.2v (for C 6a & - 75a) vdd = +2.6v 0.1v, vddq = +2.6v 0.1v (for - 5b) bi - directio nal data strobe (dqs) transmitted/ received with data, i.e. so ur ce - sy nchronous data capture (x16 has two: ldqs and udqs C one per byte) internal, pipelined double - data - rate (ddr) architecture; two data accesses per clock cycle differential clock inputs (ck and ck#) commands entered on each positive ck edge dqs edge - aligned with data for reads; center - aligned with data for writes dll to align dq and dqs transitions with ck four internal banks for concurrent operation data mask (dm) for masking write d ata (x16 has two: ldm and udm C one per byte) programmable burst lengths: 2, 4, or 8 auto precharge option auto refresh longer lead tsop for improved reliability (ocpl) 2.5v i/o (sstl_2 compatible) these devices are optimized for single r ank dimm applicat ions options : designation: family: spectek memor y saa configuration : 128 meg x 4 (32 meg x 4 x 4 banks) 128m4 64 meg x 8 (16 meg x 8 x 4 banks) 64m8 32 meg x 16 (8 meg x 16 x 4 banks) 32m16 design id: ddr2 512 megabit design tx7x (cal l spectek sales for details on availability of x placeholders) voltage and refresh : 2.5v, auto refresh v 8 2.5v, self or auto refresh r8 package types: 66 - pin plastic tsop, ocpl tw (400 mil width, 0.65mm pin pitch) 60 - ball (10mm x 12.5mm) fbga fn ti ming C cycle time : 5ns @ cl=3 (pc3200 or ddr400b) - 5b 6ns @ cl = 2.5 (pc2700 or ddr333) - 6a 7.5ns @ cl = 2.5 (pc2100 or ddr266) - 75a p art number example : saa64m8t27bv8tw - 6a ( for part numbers prior to december 2004, refer to page 12 for decoding.) pin assig nment (top view) 66 - pin tsop
512mb: x4, x8, x16 ddr sdram pdf=09005aef80c1 b136 / source=09005aef80c1a8c0 512mb: x4, x8, x16 ddr sdram rev: 11/24/2004 0 www.spectek.com spectek reserves the right to change products or specifications without notice. 2003 , 2004 spectek general description the 512mb ddr sdram is a high - speed cmos, dy namic random - access memor y c ontaining 536,870,912 bits. it is internally configured as a quad - bank dram. the 512mb ddr sdram uses a double - data rate architecture to achieve high - speed operation. the double data rate architecture is essentially a 2 n - pr efetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 512m b ddr sdram effectively consists of a single 2 n - bit wide, one - clock - cycle data transfer at the internal dram core and two corresponding n - bit wide, one - half - clock - cycle data transfers at the i/o pins. a bi - directio nal data strobe (dqs or ldqs/udqs) is tran smitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr sdram during reads and by the memory controller during writes. dqs is edge - aligned with data for reads and center - aligned with data for wri tes. the x16 offering has two data strobes, one for the lower byte and one for the upper byt e. the 512mb ddr sdram operates from a differential clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands (address and control signals) are registered at ever y positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to the ddr sd ram are burst or iented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the addr ess bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst acce ss. the ddr sdram provides for programmable read or write burst lengths of 2, 4, or 8 locations. an auto precharge function may be enabled to provide a self - timed ro w precharge that is initiated at the end of the burst access. as with standard sdr sdrams, the pipelined, multibank architecture of ddr sdrams allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. an auto refresh mode is provided, along with a power - saving power - down mode. all i nputs are compatible with the jedec standard for sstl_2. all full drive strength outputs are sstl_2, class ii compatible. note 1: the functionality and the timing specifications discussed in this data sheet are for the dll - enabled mode of operation. note 2: throughout the data sheet, the various figures and text refer to dqs as dq. the dq term is to be interpreted as any and all dq collectively, unless specifically stated otherwise. additionally, the x16 is divided in to two bytes the lower byte and upper byte. for the lower byte (dq0 through dq7) dm refers to ldm and dqs refers to ldqs; and for the upper byte (dq8 through dq15) dm refers to udm and dqs refers to udqs. ___________________________________________________ absolute maximum ratings * (vol tages relative to vss) v dd supply - 1v to +3.6v v dd q supply - 1v to +3.6v v ref and inputs - 1v to +3.6v i/o pins - 0.5v to v dd q +0.5v operating temperature, t a (ambient) 10c to +70c storage temperature (plastic) - 55c to +150c power dissipation 1w short circuit output current 50ma disclaimer: except as specifically provided in this document, spectek makes no warranties, expressed or implied, including, but not limited to, any implied warranties of merchantability or fitness for a particular purpose. any claim against spectek must be made within 1 year from the date of shipment from spectek, and spectek has no liability thereafter. any liability is limited to replacement of the defective items or return of amounts paid for defectiv e items (at buyers ele ction). in no ev ent will spectek be responsible for special, indirect, consequential or incidental damages, ev en if spectek has been advised for the possibility of such damages. specteks liability from any cause pursuant to this specification shall be l imited to general monetary damages in an amount not to exceed the total purchase price of the products cov ered by this specification, regardless of the form in which legal or equitable action may be brought against spectek.
512mb: x4, x8, x16 ddr sdram pdf=09005aef80c1 b136 / source=09005aef80c1a8c0 512mb: x4, x8, x16 ddr sdram rev: 11/24/2004 0 www.spectek.com spectek reserves the right to change products or specifications without notice. 2003 , 2004 spectek dc electrical characteristic s and operating conditions (for test conditions see note 53) parameter/condition symbol min max units notes supply voltage (for - 6a & - 75a) vdd 2.3 2.7 v 41 i/ o supply voltage (for - 6a & - 75a) vddq 2.3 2.7 v 41, 44 supply voltage (for - 5b) vdd 2.5 2.7 v 41 i/ o supply voltage (for - 5b) vddq 2.5 2.7 v 41, 44 i/ o reference voltage v ref 0.49 x v ddq 0.51 x v ddq v 6, 44 i/ o termination voltage (system) v tt v ref C 0.04 v ref + 0.04 v 7, 44 input high (logic 1) voltage v ih (dc) v ref + 0.15 v dd + 0.3 v 28 inp ut low (logic 0) voltage v il (dc) - 0.3 v ref C 0.15 v 28 clock input voltage level; ck and ck# v in - 0.3 v ddq + 0.3 v clock input differential voltage; ck and ck# v id 0.36 v ddq + 0.6 v 8 clock input crossing point voltage; ck and ck# v ix 1.15 1.35 v 9 i nput leakage current an y i nput, 0v < vin < vdd, vref pin 0v < vin < 1.35v (all other pins not under test = 0v) i i - 2 2 a output leakage current (dqs are disabled; 0v < vout < vddq) i oz - 7 7 a i oh - 16.8 -- ma output levels: full drive option - x4 , x8, x16 high cur rent (vout = vddq - 0.373v, minimum vref, minimum vtt) low current (vout = 0.373v, maximum vref, maximum vtt) i ol 16.8 -- ma 37, 39 i ohr - 9 -- ma output levels: reduced drive option - x16 only high current (vout = vddq - 0.763v, minimum vref, minimum vtt ) low current (vout = 0.763v, maximum vref, maximum vtt) i olr 9 -- ma 38, 39 ac input operating conditions (for test conditions see note 53) parameter/condition symbol min max units notes input high (logic 1) voltage v ih ( ac ) v ref + 0 .310 -- v 14, 28, 40 input low (logic 0) voltage v il ( ac ) -- v ref C 0.310 v 14, 28, 40 clock input differential voltage; ck and ck# v id ( ac ) 0.7 v ddq + 0.6 v 8 clock input crossing point voltage; ck and ck# v ix ( ac ) 0.5 x v ddq C 0.2 0.5 x v ddq + 0.2 v 9 i/ o reference voltage v ref ( ac ) 0.49 x v ddq 0.51 x v ddq v 6 capacitance (x4, x8) (for test conditions see note 53) parameter symbol min max units notes delta input/output capacitance: dqs, dqs, dm dc io -- 0.50 pf 24 delta input capacitance: comman d and address dc i 1 -- 0.50 pf 29 delta input capacitance: ck, ck# dc i 2 -- 0.25 pf 29 input/output capacitance: dqs, dqs, dm c io 4.0 5.0 pf input capacitance: command and address c i 1 2.0 3.0 pf input capacitance: ck, ck# c i 2 2.0 3.0 pf input cap acitance: cke c i 3 2.0 3.0 pf
512mb: x4, x8, x16 ddr sdram pdf=09005aef80c1 b136 / source=09005aef80c1a8c0 512mb: x4, x8, x16 ddr sdram rev: 11/24/2004 0 www.spectek.com spectek reserves the right to change products or specifications without notice. 2003 , 2004 spectek i dd specifications and conditions (x4, x8) (for test conditions see note 53) parameter/condition symbo l - 5b - 6a - 75 units notes operating current: one bank; active - precharge; t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles; i dd 0 155 135 120 ma 22, 48 operating current: one bank; active - read - precharge; burst = 2; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd 1 185 160 135 ma 22, 48 standard v parts i dd 2 p 10 10 10 ma 23, 32, 50 precharge power - down standby current: all banks idle; power - down mode; t ck = t ck(min); cke=low; self refresh r parts i dd 2 p 6 3 5 ma 23, 32, 50 precharge floating standby current: cs# = high; all banks idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs, and dm i dd 2 f 55 50 50 ma 51 active power - down standby cur rent: one bank active; power - down mode; t ck = t ck (min); cke = low i dd 3 p 45 35 25 ma 23, 32, 50 active standby current: cs# = high; cke = high; one bank; active - precharge; t rc = t ras (max); t ck = t ck (min); dq, dm, and dqs inputs changing twice per cloc k cy cle; address and other control inputs changing once per clock cycle. i dd 3 n 60 55 65 ma 22 operating current: burst = 2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i d d 4 r 190 170 155 ma 22, 48 operating current: burst = 2; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd 4 w 190 155 130 ma 22 a uto refresh current t rc = trfc (min) i dd 5 345 260 260 ma 22, 50 self refresh current (part number r only) i dd 6 6 5 4 ma 11 operating current: four bank interleaving reads (bl = 4) with auto precharge, t rc = t rc (min); t ck = t rc (min); address and con trol inputs change only during active, read, or write commands. i dd 7 450 400 335 ma 22, 49
512mb: x4, x8, x16 ddr sdram pdf=09005aef80c1 b136 / source=09005aef80c1a8c0 512mb: x4, x8, x16 ddr sdram rev: 11/24/2004 0 www.spectek.com spectek reserves the right to change products or specifications without notice. 2003 , 2004 spectek capacitance (x16) (for test conditions see note 53) parameter symbol min max units notes delta input/output capacitance: dq0 C dq7, ldqs, ldm dc iol -- 0.50 pf 24 delta input/output capacitance: dq8 - dq15, udqs, udm dc iou -- 0.50 pf 24 delta input capacitance: command and address dc i 1 -- 0.50 pf 29 delta input capacitance: ck, ck# dc i 2 -- 0.25 pf 29 input/output capacitance: dqs, ldqs, udqs, ldm, udm c io 4 .0 5.0 pf input capacitance: command and address c i 1 2.0 3.0 pf input capacitance: ck, ck# c i 2 2.0 3.0 pf input capacitance: cke c i 3 2.0 3.0 pf i dd specifications and conditions (x16) (for test conditions see note 53) parameter/condition symbo l - 5b - 6a - 75 units notes operating current: one bank; active - precharge; t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles; i dd 0 155 135 120 ma 22, 48 operating current: one bank; active - read - precharge; burst = 2; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd 1 185 160 145 ma 22, 48 standard v parts i dd 2 p 10 10 10 ma 23, 32, 50 precharge power - down standby current: all banks idle; power - down mode; t ck = t ck(min); cke=low; self refresh r parts i dd 2 p 6 3 5 ma 23, 32, 50 precharge floating standby current: cs# = high; all banks idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs, and dm i dd 2 f 55 55 55 ma 51 active power - down standby current: one bank active; power - down mode; t ck = t ck (min); cke = low i dd 3 p 45 35 25 ma 23, 32, 50 active standby current: cs# = high; cke = high; one bank; active - precharge; t rc = t ras (max); t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle. i dd 3 n 60 65 65 ma 22 operating current: burst = 2; reads; co ntinuous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd 4 r 210 190 180 ma 22, 48 operating current: burst = 2; writes; continuous burst; one bank active; address and control inputs changin g once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd 4 w 190 165 155 ma 22 auto refresh current t rc = trfc (min) i dd 5 345 260 260 ma 22, 50 self refresh current (part number r only) i dd 6 6 5 4 ma 11 operat ing current: four bank interleaving reads (bl = 4) with auto precharge, t rc = t rc (min); t ck = t rc (min); address and control inputs change only during active, read, or write commands. i dd 7 405 400 335 ma 22, 49
512mb: x4, x8, x16 ddr sdram pdf=09005aef80c1 b136 / source=09005aef80c1a8c0 512mb: x4, x8, x16 ddr sdram rev: 11/24/2004 0 www.spectek.com spectek reserves the right to change products or specifications without notice. 2003 , 2004 spectek electrical characteristics and recommended ac operating conditions (for test conditions see note 53) ac characteristics - 5b - 6a - 75 parameter symbol min min max max min max units notes access window of dqs from ck/ck# t ac - 0.70 +0.70 - 0.70 +0.70 - 0.75 +0.75 ns ck high - level width t ch 0.45 0. 55 0.45 0.55 0.45 0.55 t ck 30 ck low - level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck 30 cl = 3 t ck 5.0 7.5 ns 52 clock cycle time cl = 2.5 t ck 6.0 13 7.5 13 ns 52 dq and dm input hold time relative to dqs t dh 0.40 0.45 0.5 ns 26, 31 dq an d dm input setup time relative to dqs t ds 0.40 0.45 0.5 ns 26, 31 dq and dm input pulse width (for each input) t dipw 1.75 1.75 1.75 ns 31 access window of dqs from ck/ck# t dqsck - 0.60 +0.60 - 0.60 +0.60 - 0.75 +0.75 ns dqs input high pulse width t d qsh 0.35 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 0.35 t ck dqs - dq skew, dqs to last dq valid, per group, per access t dqsq 0.40 0.45 0.5 ns 25, 26 write command to first dqs latching transition t dqss 0.72 1.28 0.75 1.25 0.75 1.2 5 t ck dqs falling edge to ck rising C setup time t dss 0.2 0.2 0.2 t ck dqs falling edge from ck rising C hold time t dsh 0.2 0.2 0.2 t ck half clock period t hp t ch, t cl t ch, t cl t ch, t cl ns 34 data - out high - impedance window from ck/ck# t hz +0 .70 +0.70 +0.75 ns 18 data - out low - impedance window from ck/ck# t lz - 0.70 - 0.70 - 0.75 ns 18 address and control input hold time (fast slew rate) t ih f 0.6 0.75 .90 ns 14 address and control input setup time (fast slew rate) t is f 0.6 0.75 .90 n s 14 address and control input hold time (slow slew rate) t ih s 0.7 0.80 1 ns 14 address and control input setup time (slow slew rate) t is s 0.7 0.80 1 ns 14 load mode register command cycle time t mrd 10 12 15 ns dq - dqs hold, dqs to first dq to go non - valid, per access t qh thp C tqhs thp C tqhs thp C tqhs ns 25, 26 data hold skew factor t qhs 0.5 0.6 0.75 ns active to read with auto precharge command t rap na na na ns 46 active to precharge command t ras 40 16,000 42 16,000 45 16,000 n s 35 active to active/auto refresh command period t rc 55 60 65 ns auto refresh command period t rfc 70 72 75 ns 50 active to read or write delay t rcd 15 18 20 ns precharge command period t rp 15 18 20 ns dqs read preamble t rpre 0.9 1.1 0. 9 1.1 0.9 1.1 t ck 42 dqs read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck active bank a to active bank b command t rrd 10 12 15 ns dqs write preamble t wpre 0.25 0.25 0.25 t ck dqs write preamble setup time t wpres 0 0 0 ns 20, 21 dqs write po stamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck 19 write recovery time t wr 15 15 15 ns internal write to read command delay t wtr 2 1 1 t ck data valid output window na tqh - tdqsq tqh - tdqsq tqh - tdqsq ns 25 refresh to refresh command interval t refc 70.3 70.3 70.3 s 23 average periodic refresh interval t refi 7.8 7.8 7.8 s 23 terminating voltage delay to vdd t vtd 0 0 0 ns exit self refresh to non - read command (part number r only) t xsnr 75 75 75 ns exit self refresh to read comman d (part number r only) t xsrd 200 200 200 t ck
512mb: x4, x8, x16 ddr sdram pdf=09005aef80c1 b136 / source=09005aef80c1a8c0 512mb: x4, x8, x16 ddr sdram rev: 11/24/2004 0 www.spectek.com spectek reserves the right to change products or specifications without notice. 2003 , 2004 spectek notes 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operations are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load: properly initialized, and is averaged at the defined cycle rate. 4. ac timing and i dd tests may use a v il - to - v ih swing of up to 1.5v in the test en viro nme nt, but input timing is still referenced to vref (or to the crossing point for ck/ck#), and parameter specifications are guaranteed for the specified ac input levels under normal use conditio ns. the minimum slew rate for the input signals used to test the device is 1v/ns in the range bet ween v il (ac) and v ih (ac). 5. the ac and dc input level specifications areas defined in the sstl_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level, and will re main in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. v ref is expected to equal v dd q/2 of the transmitting device and to track variations in the dc level of the same. peak - to - peak noise (non - common mode) on v ref may not exceed 2 percent of the dc value. thus, from v dd q/2, v ref is allowed 25mv for dc error and an additional 25mv for ac noise. 7. v tt is not applied directly to the device. v tt is a sy stem supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 8. v id is the magnitude of the difference between the input level on ck and the input level on ck#. 9. the value of v ix is expected to equal v dd q/2 of the transmitting device and must tra ck variations in the dc level of the same. 10. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time at cl = 2.5 for C 65a and C 75a (cl=3 for C 5b) with the outputs open. 11. enables on - ch ip refresh and address co unte rs . 12. i dd specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 13. this parameter is sampled. v dd = +2.5v 0.2v, v dd q = +2.5v 0.2v, vref = v ss , f = 100 mhz, t a = 25c, v out (dc) = v dd q/2, v out (peak t o peak) = 0.2v. dm input is grouped with i/o pins, reflecting the fact that they are matched in loading. 14. command/address input slew rate = 0.5v/ns. for slew rates of 1v/ns and faster, t is and t ih are reduced to 900ps. if the slew rate is less than 0.5v/ns , timing must be derated: t is have an additional 50ps per each 100mv/ns reduction in slew rate from the 500mv/ns. t ih has 0ps added, that is, it remains constant. if the slew rate exceeds 4.5v/ns, functionality is uncertain. 15. the ck/ck# input reference leve l (for timing referenced to ck/ck#) is the point at which ck and ck# cross; the input reference level for signals other than ck/ck# is vref. 16. inputs are not recognized as valid until v ref stabilizes. exception: during the period before v ref stabilizes, cke < 0.3 x v dd q is recognized as low. 17. the output timing reference level, as measured at the timing reference point indicated in note 3, is v tt . 18. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify wh en the device output is no longer driving (hz) or begins driving (lz). 19. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but sy stem performance (bus turnaround) will degrade accordingly. 20. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 21. it is recommended that dqs be valid (high or low) on or b efore the write command. the case shown (dqs going from high - z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. 22. min ( t rc or t rfc) for i dd measurements is the smallest multiple of t ck that meets the minimum absolute value for the respective parameter. t ras (max) for i dd measurements is the largest multiple of t ck that meets the maximum absolute value for t ras. 23. the refresh period 64ms. thi s equates to an average refresh rate of 7.8125s. however, an auto refresh command must be asserted at least once ever y 70.3s; burst refreshing or posting by the dram controller greater than eight refresh cycles is not allowed. 24. the i/o capacitance per dqs and dq byte/group will not differ by more than this maximum amount for any given device.
512mb: x4, x8, x16 ddr sdram pdf=09005aef80c1 b136 / source=09005aef80c1a8c0 512mb: x4, x8, x16 ddr sdram rev: 11/24/2004 0 www.spectek.com spectek reserves the right to change products or specifications without notice. 2003 , 2004 spectek 25. the valid data window is derived by achieving other specifications - t hp ( t ck/2), t dqsq, and t qh ( t qh = t hp - t qhs). the data valid window derates directly proporti onal with the clock duty cycle and a practical data valid window can be derived. the clock is allowed a maximum duty cycle variation of 45/55. functionality is uncertain when operating beyond a 45/55 ratio. the data valid window derating curves are provide d below for duty cycles ranging between 50/50 and 45/55. 26. referenced to each output group: x4 = dqs with dq0 - dq3; x8 = dqs with dq0 - dq7; x16 = ldqs with dq0 - dq7 and udqs with dq8 - dq15. 27. this limit is actually a nominal value and does not result in a fail val ue. cke is high during refresh command period ( t rfc [min]) else cke is low (i.e., during standby). 28. to maintain a valid level, the transitioning edge of the input must: a) sustain a constant slew rate from the current ac level through to the target ac level, v il (ac) v ih (ac). b) reach at least the target ac level. c) after the ac target level is reached, continue to maintain at least the target dc level, v il (dc) or v ih (dc). 29. the input capacitance per pin group will not differ by more than this maximum amount for any given device. 30. ck and ck# input slew rate must be > 1v/ns. 31. dq and dm input slew rates must not deviate from dqs by more than 10%. if the dq/dm/dqs slew rate is less than 0.5v/ns, timing must be derated: 50ps must be added to t ds and t dh for each 100mv/ns red uction in slew rate. if slew rate exceeds 4v/ns, functionality is uncertain. 32. v dd must not vary more than 4% if cke is not active wh ile any bank is active. 33. the clock is allowed up to 150ps of jitter. each timing parameter is allowed to vary by the same amo unt. 34. t hp min is the lesser of t cl minimum and t ch minimum actually applied to the device ck and ck/ inputs, collectively during bank active. 35. reads and writes with auto precharge are not allowed to be issued until t ras (min) can be satisfied prior to the in ternal precharge command being issued. 36. applies to x16 only. first dqs (ldqs or udqs) to transitio n to last dq (dq0 - dq15) to transition valid. initial jedec specifications suggested this to be same as t dqsq. 37. note 37 is not used. 38. note 38 is not used. 39. note 39 is not used. 40. v ih overshoot: v ih (max) = v dd q+1.5v for a pulse width < 3ns and the pulse width can not be greater than 1/3 of the cycle rate. v il undershoot: v il (min) = - 1.5v for a pulse width < 3ns and the pulse width can not be greater than 1/3 of the cyc le rate. 41. v dd and v dd q must track each other. 42. note 42 is not used. 43. note 43 is not used. 44. during initialization, v dd q, v tt , and v ref must be equal to or less than v dd + 0.3v. alternatively, v tt may be 1.35v maximum during power up, even if v dd /v dd q are 0 vol ts, provided a minimum of 42 ohms of series resistance is used between the v tt supply and the input pin. 45. note 45 is not used. 46. t rap > t rcd. 47. note 47 is not used. 48. random addressing changing 50% of data changing at ever y tr ansfer. 49. random addressing changing 10 0% of data changing at ever y tr ansfer. 50. cke must be active (high) during the entire time a refresh command is executed. that is, from the time the auto refresh command is registered, cke must be active at each rising clock edge, until t ref later. 51. i dd 2n spec ifies the dq, dqs, and dm to be driven to a valid high or low logic level. i dd 2q is similar to i dd 2f except i dd 2q specifies the address and control inputs to remain stable. although i dd 2f, i dd 2n, and i dd 2q are similar, i dd 2f is worst case. 52. whenever the o perating frequency is altered, not including jitter, the dll is required to be reset. this is followed by 200 clock cycles . 53. for - 6a & - 75a; 10c < ta < +70c; vdd/vddq = +2.5v 0.2v. for - 5b; 10c < ta < +70c; vdd/vddq = +2.6v 0.1v.
512 mb: x4, x8, x16 ddr sdram pdf=09005aef80c1 b136 / source=09005aef80c1a8c0 512mb: x4, x8, x16 ddr sdram rev: 11/24/2004 9 www.spectek.com spectek reserves the right to change products or specifications without notice. 2003 , 2004 spectek 6 6 - pin plastic tsop (400mil)
512 mb: x4, x8, x16 ddr sdram pdf=09005aef80c1 b136 / source=09005aef80c1a8c0 512mb: x4, x8, x16 ddr sdram rev: 11/24/2004 10 www.spectek.com spectek reserves the right to change products or specifications without notice. 2003 , 2004 spectek ball assignment (top view) 60 - ball fbga
512 mb: x4, x8, x16 ddr sdram pdf=09005aef80c1 b136 / source=09005aef80c1a8c0 512mb: x4, x8, x16 ddr sdram rev: 11/24/2004 11 www.spectek.com spectek reserves the right to change products or specifications without notice. 2003 , 2004 spectek 60 - ball fbga (10mm x 12.5mm) note: all dimensions in millimeters.
512 mb: x4, x8, x16 ddr sdram pdf=09005aef80c1 b136 / source=09005aef80c1a8c0 512mb: x4, x8, x16 ddr sdram rev: 11/24/2004 12 www.spectek.com spectek reserves the right to change products or specifications without notice. 2003 , 2004 spectek part numbers for pro duct prior to de cember 2004 options marking configuration 128 meg x 4 (32 meg x 4 x 4 banks) s40128 64 meg x 8 (16 meg x 8 x 4 banks) s80064 32 meg x 16 (8 meg x 16 x 4 banks) s160032 voltage and refresh 2.5v, auto refresh vm 2.5v, self or auto refresh rm parent devic e configuration 128 meg x 4 k 64 meg x 8 j 32 meg x 16 l package 66 - pin plastic tsop, ocpl tw (400 mil width, 0.65mm pin pitch) 60 - ball (10mm x 12.5mm) fbga fn timing C cycle time 5ns @ cl=3 (pc3200 or ddr400b) - 5b 6ns @ cl = 2.5 (pc2700 or ddr333) - 6a 7 .5ns @ cl = 2.5 (pc2100 or ddr266) - 75a (example part number: s80064vmjtw - 6a ) http://www.spectek.com/menus/part_guides.asp

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